Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture

Table 1

All-digital frequency multiplier architectures comparison.

Proposed D/FLL architecture
Advantages
(i) No phase error accumulation.
(ii) The multiplication factor is controllable.
(iii) Portable.
Disadvantages
(i) Dual-loop architecture.
ADPLL [3, 5]
Advantages
(i) Single-loop architecture.
(ii) Able to achieve wide lock range.
Disadvantages
(i) Phase error accumulation.
(ii) Frequency fine tuning mechanism is challenging.
ADDLL [2, 4]
Advantages
(i) Single-loop architecture.
(ii) No phase error accumulation.
Disadvantages
(i) Limited phase capturing range.
(ii) The multiplication factor is not controllable.
(iii) Edge combining circuit is needed.
(iv) Any mismatch in the edge combining logic will be translated directly into a duty-cycle error and fixed-pattern jitter.