Research Article
Redundant Logic Insertion and Latency Reduction in Self-Timed Adders
Table 3
Delay, area, and power metrics of various redundant 32-bit self-timed RCAs.
| | Adder realization style | Delay (ns) | Area (μm2) | Power (μW) |
| | SSSC_HIE_RL (weak) | 5.9 | 6953 (88) | 630.2 | | DIMS_DSSC_DRE (weak) [25] | 10.5 | 22473 (1242) | 1034.6 | | Folco et al._DSSC_DRE (weak) [34] | 4.7 | 9577 (436) | 743.8 | | DSSC_DRE (weak) | 4.6 | 15081 (780) | 875.3 | | DSSC_HE (weak) | 4.6 | 11049 (412) | 691.9 |
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