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VLSI Design
Volume 2012 (2012), Article ID 580584, 16 pages
Research Article

Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper

1Department of Electrical and Electronic Engineering, University of Cagliari, 09123 Cagliari, Italy
2Silicon Hive B.V., High Tech Campus, 5656AE Eindhoven, The Netherlands

Received 15 September 2011; Revised 22 December 2011; Accepted 22 December 2011

Academic Editor: Lech Jozwiak

Copyright © 2012 Paolo Meloni et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [2 citations]

The following is the list of published articles that have cited the current article.

  • Francesca Palumbo, Carlo Sau, and Luigi Raffo, “Coarse-grained reconfiguration: dataflow-based power management,” Iet Computers And Digital Techniques, vol. 9, no. 1, pp. 36–48, 2015. View at Publisher · View at Google Scholar
  • Francesca Palumbo, Tiziana Fanni, Carlo Sau, and Paolo Meloni, “Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy,” Journal of Signal Processing Systems, 2016. View at Publisher · View at Google Scholar