Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper

Table 3

FPGA hardware overhead figures.

	Occupied slices	Slice registers	Slice LUTs
Largest configuration	19859	6923	16387
WCC	21278	6931	17951
	(+7.1%)	(+0.001%)	(+9.5%)