Hardware Design Considerations for Edge-Accelerated Stereo Correspondence Algorithms

Table 9

Hardware overheads of the edge-directed ADSW-based architecture (System 4) (image size = 800 × 600, max disparity range = 64, support window size = 11 × 11).

Design unit	Slice LUTs	Slice registers	Block RAMs	DSP48Es	Frequency
	(69120)	(69120)	(148)	(64)	(MHz)
rgb2gray	0	0	3 (~4.7%)	0	N/A
rgb2yuv	261 (~0.4%)	0	0	0	N/A
Weight generator	7056 (~10.2%)	0	0	0	N/A
Cost aggregator	30691 (~44.4%)	434 (~0.6%)	0	0	391
WTA	83 (~0.1%)	61 (~0.1%)	0	0	429
On-chip MA (left)	228 (~0.3%)	2304 (~3.3%)	0	0	632
On-chip MA (right)	644 (~0.9%)	2574 (~3.7%)	0	0	582
Canny detector	2060 (~3%)	947 (~1.4%)	0	0	165
Microblaze system & external memory Controller	7754 (~11.2%)	8562 (~12.4%)	6 (~9.4%)	30 (~20.3%)	161
Complete system	50539 (~73.1%)	44802 (~64.8%)	12 (~18.8%)	30 (~20.3%)	155