Table of Contents Author Guidelines Submit a Manuscript
VLSI Design
Volume 2012, Article ID 730835, 16 pages
http://dx.doi.org/10.1155/2012/730835
Review Article

Flexible LDPC Decoder Architectures

Department of Electronics and Telecommunications, Politecnico di Torino, 10129 Torino, Italy

Received 4 November 2011; Revised 14 February 2012; Accepted 22 February 2012

Academic Editor: Amer Baghdadi

Copyright © 2012 Muhammad Awais and Carlo Condo. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Flexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard. A flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However, the design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power constraints is a challenging task and still requires considerable research effort. This paper provides an overview of state-of-the-art in the design of flexible LDPC decoders. The published solutions are evaluated at two levels of architectural design: the processing element (PE) and the interconnection structure. A qualitative and quantitative analysis of different design choices is carried out, and comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumption.