Flexible LDPC Decoder Architectures

Table 5

Flexible LDPC decoders ASIP Implementations. CMOS technology process (Tech), area occupation (A), normalized area (A_norm)@ 130 nm, code type (C.T), flexibility (Flex.) design time (D.T), run time (R.T), maximum throughput (T.P), maximum iterations (It.), number of datapaths (Dp), operating frequency (𝑓), processing element (PE) (serial Se, parallel Pa), throughput area ratio (TAR)(Mb/s × It/mm² = t.p × It/A_norm), and decoding efficiency (DE) (bits/cycle = t.p × It/𝑓).

Design

Tech. (nm)

A mm^2

Anorm mm^2

C.T

Flex.

It.

T.P Mb/s

F MHz.

Dp

PE

TAR

DE

Multicore ASIP [39]

90

2.6

5.42

LDPC-{WiMAX,WiFi}; Turbo-{BTC-LTE,DBTC-WiMAX}

R.T

10; 6

{312,263}; {173,173}

500

24

Se

{575.6,485.2}; {191.4,191.4}

{6.24,5.26}; {2.07,2.07}

2D NOC ASIP [40]

130

N/A

N/A

Turbo; LDPC

R.T

8

86.5; 11.2

200

16

Se

N/A

3.46; 0.448

FlexiCHAP [41]

65

0.62

2.48

LDPC-{WiMAX, WiFi}; Turbo {BTC,DBTC}

R.T

10–20; 5

{237,257}; {18.6,37.2}

400 (max.)

27

Se

{955.6,1036.3}; {37.5,75.0}

{5.9,6.42}; {0.23,0.46}

Bin/non-Bin [42]

65

3.4

13.6

Bin LDPC-{WiMAX, WiFi}; Non-Bin LDPC {GF(9)}

R.T

10; 1

90; 12.5

400

96

Se

66.2; 0.92

2.25; 0.03