VLSI Design

VLSI Design / 2012 / Article / Tab 1

Research Article

Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm

Table 1

7 valued logic.


S0Steady 0
S1Steady 1
T0Falling transition
T1Rising transition
P0Positive glitch
P1Negative glitch
XUnknown value

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