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VLSI Design
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2012
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Article
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Tab 1
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Research Article
Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm
Table 1
7 valued logic.
Signal
Description
S0
Steady 0
S1
Steady 1
T0
Falling transition
T1
Rising transition
P0
Positive glitch
P1
Negative glitch
X
Unknown value