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VLSI Design
Volume 2012, Article ID 752024, 13 pages
Research Article

𝑁 Point DCT VLSI Architecture for Emerging HEVC Standard

Department of Electronics & Telecommunication, Politecnico di Torino, 10129 Torino, Italy

Received 21 December 2011; Revised 13 April 2012; Accepted 6 May 2012

Academic Editor: Andrey Norkin

Copyright © 2012 Ashfaq Ahmed et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This work presents a flexible VLSI architecture to compute the 𝑁 -point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, 4 × 4 up to 3 2 × 3 2 , the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into sparse submatrices in order to reduce the multiplications. Finally, multiplications are completely eliminated using the lifting scheme. The proposed architecture sustains real-time processing of 1080P HD video codec running at 150 MHz.