Table of Contents
VLSI Design
Volume 2012, Article ID 793196, 11 pages
http://dx.doi.org/10.1155/2012/793196
Research Article

An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C

School of Engineering and Computer Science, University of Guelph, Guelph, ON, Canada N1G 2W1

Received 4 March 2011; Revised 4 August 2011; Accepted 1 October 2011

Academic Editor: Gregory Peterson

Copyright © 2012 M. Walton et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Scatter Search is an effective and established population-based metaheuristic that has been used to solve a variety of hard optimization problems. However, the time required to find high-quality solutions can become prohibitive as problem sizes grow. In this paper, we present a hardware implementation of Scatter Search on a field-programmable gate array (FPGA). Our objective is to improve the run time of Scatter Search by exploiting the potentially massive performance benefits that are available through the native parallelism in hardware. When implementing Scatter Search we employ two different high-level languages (HLLs): Handel-C and Impulse-C. Our empirical results show that by effectively exploiting source-code optimizations, data parallelism, and pipelining, a 28x speed up over software can be achieved.