Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors

<table>Example of the hierarchical communication network of LDPC decoders for IEEE 802.15.3c LDPC code decoder of 1/2 rate (R), code length 672 (L), and (micro, macro) parallelism of (1,84).</table>

VLSI Design

fig9

Figure 9

Figure 9: Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors 