Table of Contents
VLSI Design
Volume 2012, Article ID 870546, 15 pages
Research Article

Power Consumption Models for Decimation FIR Filters in Multistandard Receivers

1Cirta’com Laboratory, Ecole Supérieure des Communications de Tunis, 2083 Ariana, Tunisia
2IMS Laboratory, Université de Bordeaux I, Bordeaux, 33405 Talence, France

Received 3 December 2011; Revised 9 March 2012; Accepted 15 March 2012

Academic Editor: Frank Kienle

Copyright © 2012 Khaled Grati et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [3 citations]

The following is the list of published articles that have cited the current article.

  • Syeda Zahra Naqvi, Syed Zulqadar Hassan, and Tariq Kamal, “A power consumption and area improved design of IIR decimation filters via MDT,” 2016 International Conference on Intelligent Systems Engineering (ICISE), pp. 146–151, . View at Publisher · View at Google Scholar
  • Farid Shamani, Roberto Airoldi, Vida Fakour Sevom, Tapani Ahonen, and Jari Nurmi, “FPGA Implementation Issues of a Flexible Synchronizer Suitable for NC-OFDM-Based Cognitive Radios,” Journal of Systems Architecture, vol. 76, pp. 102–116, 2017. View at Publisher · View at Google Scholar
  • Jyoti, Adesh Kumar, and Anil Sangwan, “Designing of FIR Filter Using FPGA: A Review,” Nanoelectronics, Circuits and Communication Systems, vol. 511, pp. 493–505, 2018. View at Publisher · View at Google Scholar