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VLSI Design
Volume 2012 (2012), Article ID 942893, 10 pages
Review Article

Design Space of Flexible Multigigabit LDPC Decoders

1Microelectronic Systems Design Research Group, University of Kaiserslautern, 67663 Kaiserslautern, Germany
2R&D Department, Creonic GmbH, 67655 Kaiserslautern, Germany

Received 2 December 2011; Accepted 7 February 2012

Academic Editor: Guido Masera

Copyright © 2012 Philipp Schläfer et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [2 citations]

The following is the list of published articles that have cited the current article.

  • Meng Li, Yanxiang Huang, Youngjoo Lee, and Liesbet Van Der Perre, “Area and energy efficient 802.11ad LDPC decoding processor,” Electronics Letters, vol. 51, no. 4, pp. 339–341, 2015. View at Publisher · View at Google Scholar
  • Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, and Predrag Spasojevic, “FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis,” International Journal of Reconfigurable Computing, vol. 2017, pp. 1–23, 2017. View at Publisher · View at Google Scholar