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VLSI Design
Volume 2012, Article ID 942893, 10 pages
http://dx.doi.org/10.1155/2012/942893
Review Article

Design Space of Flexible Multigigabit LDPC Decoders

1Microelectronic Systems Design Research Group, University of Kaiserslautern, 67663 Kaiserslautern, Germany
2R&D Department, Creonic GmbH, 67655 Kaiserslautern, Germany

Received 2 December 2011; Accepted 7 February 2012

Academic Editor: Guido Masera

Copyright © 2012 Philipp Schläfer et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [10 citations]

The following is the list of published articles that have cited the current article.

  • Philipp Schlafer, Norbert Wehn, Matthias Alles, and Timo Lehnigk-Emden, “A new dimension of parallelism in ultra high throughput LDPC decoding,” SiPS 2013 Proceedings, pp. 153–158, . View at Publisher · View at Google Scholar
  • Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, and Predrag Spasojevic, “High-Throughput FPGA-Based QC-LDPC Decoder Architecture,” 2015 IEEE 82nd Vehicular Technology Conference (VTC2015-Fall), pp. 1–5, . View at Publisher · View at Google Scholar
  • Alexios Balatsoukas-Stimming, and Apostolos Dollas, “FPGA-based design and implementation of a multi-GBPS LDPC decoder,” Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012, pp. 262–269, 2012. View at Publisher · View at Google Scholar
  • Christina Gimmler-Dumont, Philipp Schlafer, and Norbert Wehn, “FPGA-based rapid prototyping platform for MIMO-BICM design space exploration,” 2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012, 2012. View at Publisher · View at Google Scholar
  • Frank Kienlevol. 9781461480303, pp. 1–260, 2014. View at Publisher · View at Google Scholar
  • Meng Li, Yanxiang Huang, Youngjoo Lee, and Liesbet Van Der Perre, “Area and energy efficient 802.11ad LDPC decoding processor,” Electronics Letters, vol. 51, no. 4, pp. 339–341, 2015. View at Publisher · View at Google Scholar
  • Schlafer, Wehn, Scholl, and Leonardi, “A new LDPC decoder hardware implementation with improved error rates,” 2015 IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies, AEECT 2015, 2015. View at Publisher · View at Google Scholar
  • Norbert Wehn, Stefan Scholl, Philipp Schläfer, Timo Lehnigk-Emden, and Matthias Allespp. 7–31, 2015. View at Publisher · View at Google Scholar
  • Liesbet Van Der Perre, Steven Dupont, Peter Debacker, Andy Dewilde, Meng Li, Wim Van Thillo, Jan-Willem Weijers, Veerle Derudder, Ilse Vos, Maxim Rykunov, and Yanxiang Huang, “An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS,” 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings, 2016. View at Publisher · View at Google Scholar
  • Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, and Predrag Spasojevic, “FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis,” International Journal of Reconfigurable Computing, vol. 2017, pp. 1–23, 2017. View at Publisher · View at Google Scholar