Review Article
Design Space of Flexible Multigigabit LDPC Decoders
Table 2
Multigigabit decoder evolution.
| | | This paper | WPAN [17] | This paper | WPAN [18] | WiGig [19] | WPAN [20] |
| Standard | | WiMedia 1.5-based | IEEE 802.15.3c draft | IEEE 802.15.3c | IEEE 802.15.3c | IEEE 802.11ad | IEEE 802.15.3c | Technology | | 65 nm | 65 nm | 65 nm | 65 nm | 65 nm | 65 nm | Postplace and route | | No | No | Yes | Yes | No | Yes | Codeword length | |
600
|
576
|
672
|
672
|
672
|
672
| Code rates | | , , , | , , | , , , | , , , | , , , | , , , | Submatrix size | |
15
|
18
|
21
|
21
|
42
|
21
| Edges/cycle | |
45
|
288
|
336
|
672
|
672
|
672
| [MHz] | |
400
|
500
|
500
|
197
|
150
|
400
| Scheduling | | Layered | Two-phase | Two-phase | Layered | Two-phase | Layered | Algorithmic iterations | |
5
|
7
|
9
|
4
| N/A |
9
| Cycles/iteration | | 40–45 |
10
|
11
|
4
|
4
|
4
| Pipeline stages | |
3
|
2
|
3
|
0
|
4
|
4
| Frame interleaved | | No | No | No | No | Yes | Yes | Input quantization | |
6
|
6
|
5
|
6
| N/A |
6
|
| Hardware mapping | | Other | Column-based | Column-based | Row-based | Row-based | Row-based | VNU degree | |
1
|
4
|
4
|
1
|
1
|
1
| CNU degree | |
3
| 1–4 | 1–4 | 8–32 | 8–16 | 8–32 | VNU instances | |
45
|
72
|
84
|
672
|
672
| 672 | CNU instances | |
15
| 72–288 | 84–336 | 21–84 | 42–84 | 21–84 |
| Logic Area | | | N/A | | N/A | N/A | | Memory area | | | N/A | | N/A | N/A | | Area [ ] | |
0.37
|
0.50
|
1.15
|
1.56
|
1.30
|
1.30
|
| Supply [V] | |
1.2
| N/A |
1.2
|
1.0
|
0.8
|
1.2
| Power [mW] | | N/A | N/A |
630
|
361
|
84
|
538
| Energy eff. [pJ/bit/Iter] | | N/A | N/A |
21
|
13
|
7
|
8
|
| Thr. [Gbit/s/ ] | |
2.62
|
7.20
|
2.66
|
3.24
|
2.37
|
5.17
| Thr. [bit/Cycle] | |
2.43
|
7.20
|
6.11
|
33.60
|
20.50
|
16.80
| Thr. Air [Gbit/s] | |
0.97
|
3.60
|
3.06
|
6.62
|
3.08
|
6.72
|
|
|