VLSI Design

VLSI Design / 2012 / Article / Tab 2

Research Article

Low-Complexity Hardware Interleaver/Deinterleaver for IEEE 802.11a/g/n WLAN

Table 2

Implementation details and comparison results.

IWCMC’05 [16]ASICON’09 [13]ISCAS’09 [14]This work

FunctionInt.Int. & Deint.Int. & Deint.Int. & Deint.
StandardWWiSE Proposal to802.11n802.11n802.11n802.11a/g/n
Parallel streams1141
Parallel bits24366
Technology0.18 μm0.13 μm65 nm0.13 μm
Ping-pang bufferYesYesNoYes
Memory area (μm2)564587536302513663273
AGU and logic area (μm2)1686581127096907049
AGU number1131
Total area (μm2)733245649003482470322
Max frequency (MHz)200350225400
Normalized complexity5.2050.6670.7650.417

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