Research Article
Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL
Table 1
Transistors sizes used in each design block of the DPTAAL full adder.
| | Design blocks | PMOS | NMOS | Minimum length
(m) | Width (m) | Minimum length
(m) | Width (m) |
| | Adiabatic DPL gates, MUX, and buffer | 0.18 | 5.0 | 0.18 | 5.0 | | C&R section | 0.18 | 5.0 | 0.18 | 2.0 |
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