Research Article
Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL
Table 6
Process parameters used for this simulation.
| | Parameters | Value |
| | Process technology | 0.18 m | | Supply voltage () | 1.8 V | | Ambient temperature | 0–70°C | | Gate oxide thickness () | 4 nm | | Gate capacitance () | 2 fF/μm2 | | Minimum gate length () | 0.18 μm | | NFET threshold voltage () | 0.39 V | | PFET threshold voltage () | −0.42 V | | NFET drain current () | 600 mA | | PFET drain current () | 260 mA |
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