VLSI Design

VLSI Design / 2013 / Article / Fig 21

Research Article

Energy-Efficient Hardware Architectures for the Packet Data Convergence Protocol in LTE-Advanced Mobile Terminals

Figure 21

Area consumption of the LSB coprocessor with parallel and loop implementations.
369627.fig.0021

We are committed to sharing findings related to COVID-19 as quickly and safely as possible. Any author submitting a COVID-19 paper should notify us at help@hindawi.com to ensure their research is fast-tracked and made available on a preprint server as soon as possible. We will be providing unlimited waivers of publication charges for accepted articles related to COVID-19.