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VLSI Design
Volume 2013, Article ID 382682, 10 pages
http://dx.doi.org/10.1155/2013/382682
Research Article

FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders

Department of Electrical Engineering, The University of Texas at Tyler, Tyler, TX 75799, USA

Received 5 August 2013; Accepted 19 September 2013

Academic Editor: Chien-Min Ou

Copyright © 2013 David H. K. Hoe et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

David H. K. Hoe, L. P. Deepthi Bollepalli, and Chris D. Martinez, “FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders,” VLSI Design, vol. 2013, Article ID 382682, 10 pages, 2013. https://doi.org/10.1155/2013/382682.