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VLSI Design
Volume 2013, Article ID 382682, 10 pages
http://dx.doi.org/10.1155/2013/382682
Research Article

FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders

Department of Electrical Engineering, The University of Texas at Tyler, Tyler, TX 75799, USA

Received 5 August 2013; Accepted 19 September 2013

Academic Editor: Chien-Min Ou

Copyright © 2013 David H. K. Hoe et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. Spartan 3 Generation User Guide, http://www.xilinx.com/support/documentation/user_guides/ug331.pdf.
  2. D. H. K. Hoe, C. Martinez, and S. J. Vundavalli, “Design and characterization of parallel prefix adders using FPGAs,” in Proceedings of the 43rd IEEE Southeastern Symposium on System Theory (SSST '11), pp. 168–172, Auburn, Ala, USA, March 2011. View at Publisher · View at Google Scholar · View at Scopus
  3. C. D. Martinez, L. P. D. Bollepalli, and D. H. K. Hoe, “A fault tolerant parallel-prefix adder for VLSI and FPGA design,” in Proceedings of the 44th IEEE Southeastern Symposium on System Theory (SSST '12), pp. 121–125, Jacksonville, Fla, USA, March 2012.
  4. S. Ghosh, P. Ndai, and K. Roy, “A novel low overhead fault tolerant Kogge-Stone adder using adaptive clocking,” in Proceedings of the Design, Automation and Test in Europe (DATE '08), pp. 366–371, Munich, Germany, March 2008. View at Publisher · View at Google Scholar · View at Scopus
  5. P. M. Kogge and H. S. Stone, “A parallel algorithm for the efficient solution of a general class of recurrence equations,” IEEE Transactions on Computers, vol. 22, no. 8, pp. 786–793, 1973. View at Google Scholar · View at Scopus
  6. Xilinx Inc, http://www.xilinx.com.
  7. Altera Corporation, http://www.altera.com/.
  8. R. P. Brent and H. T. Kung, “A regular layout for parallel adders,” IEEE Transactions on Computers, vol. 31, no. 3, pp. 260–264, 1982. View at Google Scholar · View at Scopus
  9. N. H. E. Weste and D. M. Harris, CMOS VLSI Design, Pearson, Addison-Wesley, 4th edition, 2011.
  10. D. Harris, “A taxonomy of parallel prefix networks,” in Proceedings of the 37th Asilomar Conference on Signals, Systems and Computers, pp. 2213–2217, Pacific Grove, Calif, USA, November 2003. View at Scopus
  11. E. Stott, P. Sedcole, and P. Y. K. Cheung, “Fault tolerant methods for reliability in FPGAs,” in Proceedings of the International Conference on Field Programmable Logic and Applications, pp. 415–420, Heidelberg, Germany, September 2008. View at Publisher · View at Google Scholar · View at Scopus
  12. M. Abramovici and C. Stroud, “BIST-based detection and diagnosis of multiple faults in FPGAs,” in Proceedings of the International Test Conference, pp. 785–794, Atlantic City, NJ, USA, October 2000. View at Publisher · View at Google Scholar
  13. L. Zhao, D. M. H. Walker, and F. Lombardi, “IDDQ testing of bridging faults in logic resources of reconfigurable field programmable gate arrays,” IEEE Transactions on Computers, vol. 47, no. 10, pp. 1136–1152, 1998. View at Publisher · View at Google Scholar · View at Scopus
  14. Xilinx TMR Tool, http://www.xilinx.com/ise/optional_prod/tmrtool.htm.
  15. L. Sterpone and M. Violante, “Analysis of the robustness of the TMR architecture in SRAM-based FPGAs,” IEEE Transactions on Nuclear Science, vol. 52, no. 5, pp. 1545–1549, 2005. View at Publisher · View at Google Scholar · View at Scopus
  16. F. L. Kastensmidt, L. Sterpone, L. Carro, and M. S. Reorda, “On the optimal design of triple modular redundancy logic for SRAM-based FPGAs,” in Proceedings of the Design, Automation and Test in Europe (DATE '05), pp. 1290–1295, Munich, Germany, March 2005. View at Publisher · View at Google Scholar · View at Scopus
  17. M. G. Gericota, L. F. Lemos, G. R. Alves, and J. M. Ferreira, “On-line self-healing of circuits implemented on reconfigurable FPGAs,” in Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS '07), pp. 217–222, Crete, Greece, July 2007. View at Publisher · View at Google Scholar · View at Scopus
  18. M. Abramovici, J. M. Emmert, and C. E. Stroud, “Roving STARs: an integrated approach to on-line testing, diagnosis, and fault tolerance for FPGAs in adaptive computing systems,” in Proceedings of the 3rd NASA/DoD Workshop on Evolvable Hardware, pp. 73–92, Long Beach, Calif, USA, July 2001.
  19. J. M. Emmert, C. E. Stroud, and M. Abramovici, “Online fault tolerance for FPGA logic blocks,” IEEE Transactions on Very Large Scale Integration Systems, vol. 15, no. 2, pp. 216–226, 2007. View at Publisher · View at Google Scholar · View at Scopus
  20. F. Hatori, T. Sakurai, K. Nogami et al., “Introducing redundancy in field programmable gate arrays,” in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC '93), pp. 7.1.1–7.1.4, San Diego, Calif, USA, May 1993. View at Publisher · View at Google Scholar · View at Scopus
  21. V. Lakamraju and R. Tessier, “Tolerating operational faults in cluster-based FPGAs,” in Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '00), pp. 187–194, Monterey, Calif, USA, February 2000. View at Scopus
  22. J. M. Emmert and D. Bhatia, “Partial reconfiguration of FPGA mapped designs with applications for fault tolerance and yield enhancement,” in Proceedings of the 7th International Workshop on Field Programmable Logic and Applications, vol. 1304, pp. 141–150, Lecture Notes in Computer Science, London, UK, September 1997.
  23. Y. Nakamura and K. Hiraki, “Highly fault-tolerant FPGA processor by degrading strategy,” in Proceedings of the 2002 Pacific Rim International Symposium on Dependable Computing, pp. 75–78, Tsukuba, Japan, December 2002.
  24. J. A. Cheatham, J. M. Emmert, and S. Baumgart, “A survey of fault tolerant methodologies for FPGAs,” ACM Transactions on Design Automation of Electronic Systems, vol. 11, no. 2, pp. 501–533, 2006. View at Publisher · View at Google Scholar · View at Scopus