Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor

Table 1

Hazard-1. Type-1: RAW.

Dependent register	Instruction
EX.Register	AND, OR, NOT, XOR, ADD, SUB, MUL, MOV
ID.Register.Source	AND, OR, NOT, XOR, ADD, SUB, MUL, MOV