Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor

Table 5

The instruction set format.

(a) Direct/Indirect Address Mode (bit location)

OPCODE		ADDMODE		TARGET		SOURCE		NOTHING
15	12	11	10	9	6	5	2	1	0

(b) Immediately Address Mode (bit location)

OPCODE		ADDMODE		TARGET		IMMEDICATE
15	12	11	10	9	6	5	0

(c)  

Instruction	Function	Direct address mode	Immediately address mode	Indirect address mode	Comments
AND	AND operation	AND R0, R1	AND R0, #10	AND R0, @R1	R0=R0⋅R1
OR	OR operation	OR R0, R1	OR R0, #10	OR R0, @R1	R0=R0+R1
NOT	NOT operation	NOT R0			R0=R0^′
XOR	Exclusive OR	XOR R0, R1	XOR R0, #10	XOR R0, @R1	R0=R0⊕R1
ADD	Addition	ADD R0, R1	ADD R1, #10	ADD R0, @R1	R0=R0+R1
SUB	Subtract	SUB R0, R1	SUB R0, #10	SUB R0, @R1	R0=R0−R1
MUL	Multiply	MUL R0, R1			{R0,R1}=R0∗R1
MOV	Move	MOV R0, R1	MOV R0, #10	MOV R0, @R1	R0 ← R1
JMP	Jump		JMP #10		PC value change
JGE	Condition jump		JGE #10		PC value change
CMP	Comparison	CMP R0, R1
NOP	No operation				No operation
STA	Store to memory	STA M[R0], R1	STA M[0], R1		M[R0] ← R1
LDA	Load from memory	LDA R0, M[R1]	LDA R0, M[0]		R0 ← M[R1]