Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor

Table 6

The instruction action table.

Instruction	Operation
	Fetch	Decode	Execution	Writeback
JMP	A	A	—	—
CMP	A	—	A	—
JGE	A	A	—	—
NOP	A	—	—	—
STA	A	A	—	—