Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor

Table 9

Hazard-3. Type-1: RAW, WAW.

Dependent register	Instruction
EX.Register	LDA
ID.Register.Source	STA

Ex: LDA r0, m[1] → STA m[2], r0, RAW at r0.
LDA r0, m[1] → STA m[r0], r1, WAW at r0.