Table of Contents Author Guidelines Submit a Manuscript
VLSI Design
Volume 2013, Article ID 474601, 15 pages
http://dx.doi.org/10.1155/2013/474601
Research Article

Fast and Near-Optimal Timing-Driven Cell Sizing under Cell Area and Leakage Power Constraints Using a Simplified Discrete Network Flow Algorithm

Department of ECE, University of Illinois at Chicago, Chicago, IL 60607, USA

Received 24 May 2012; Revised 6 November 2012; Accepted 21 November 2012

Academic Editor: Gi-Joon Nam

Copyright © 2013 Huan Ren and Shantanu Dutt. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. C. P. Chen, C. C. N. Chu, and D. F. Wong, “Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 7, pp. 1014–1025, 1999. View at Publisher · View at Google Scholar · View at Scopus
  2. J. Fishburn and A. Dunlop, “Tilos: a posynomial programming approach to transistor sizing,” in Proceedings of International Conference on Computer-Aided Design, pp. 326–328, 1985.
  3. S. Hu, M. Ketkar, and J. Hu, “Gate sizing for cell library-based designs,” in Proceedings of the 44th ACM/IEEE Design Automation Conference (DAC '07), pp. 847–852, June 2007. View at Publisher · View at Google Scholar · View at Scopus
  4. F. Beeftink, P. Kudva, D. Kung, and L. Stok, “Gate-size selection for standard cell libraries,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD '98), pp. 545–550, November 1998. View at Scopus
  5. O. Coudert, “Gate sizing for constrained delay/power/area optimization,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 5, no. 4, pp. 465–472, 1997. View at Google Scholar · View at Scopus
  6. M. M. Ozdal, S. Burns, and J. Hu, “Gate sizing and device technology selection algorithms for high-performance industrial designs,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD '11), pp. 724–731, November 2011.
  7. S. Dutt and H. Ren, “Discretized network flow techniques for timing and wire-length driven incremental placement with white-space satisfaction,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 7, pp. 1277–1290, 2011. View at Publisher · View at Google Scholar · View at Scopus
  8. H. Ren and S. Dutt, “A provably high-probability white-space satisfaction algorithm with good performance for standard-cell detailed placement,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 7, pp. 1291–1304, 2011. View at Publisher · View at Google Scholar · View at Scopus
  9. S. Dutt, H. Ren, F. Yuan, and V. Suthar, “A network-flow approach to timing-driven incremental placement for ASICs,” in Proceedings of the International Conference on Computer-Aided Design (ICCAD '06), pp. 375–382, November 2006. View at Publisher · View at Google Scholar · View at Scopus
  10. U. Brenner, “VLSI legalization with minimum perturbation by iterative augmentation,” in Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE '12), pp. 1385–1390, March 2012.
  11. H. Ren and S. Dutt, “A network-flow based cell sizing algorithm,” in Proceedings of the 17th International Workshop on Logic & Synthesis, pp. 7–14, 2008.
  12. S. Dutt and H. Ren, “Timing yield optimization via discrete gate sizing using globally-informed delay PDFs,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD '10), pp. 570–577, November 2010.
  13. H. Ren and S. Dutt, “Effective power optimization under timing and voltage-island constraints via simultaneous VDD, Vth assignments, gate sizing, and placement,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 5, pp. 746–759, 2011. View at Publisher · View at Google Scholar · View at Scopus
  14. H. Ren and S. Dutt, “Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD '08), November 2008.
  15. A. Nahapetyan and P. M. Pardalos, “A bilinear relaxation based algorithm for concave piecewise linear network flow problems,” Journal of Industrial and Management Optimization, vol. 3, no. 1, pp. 71–85, 2007. View at Google Scholar · View at Scopus
  16. R. K. Ahuja, T. L. Magnanti, and J. B. Orlin, Network Flows: Theory, Algorithms, and Applications, chapter 10-11, Prentice-Hall, Upper Saddle River, NJ, USA, 1993.
  17. D. Kim and P. Pardalos, “Gate sizing in MOS digital circuits with linear programming,” in Proceedings of the Conference on European Design Automation (EURO-DAC '90), pp. 217–221, 1990.
  18. R. K. Ahuja and J. B. Orlin, “Scaling network simplex algorithm,” Operations Research, vol. 40, supplement 1, pp. S5–S13, 1992. View at Publisher · View at Google Scholar
  19. I. Adler and N. Megiddo, “A simplex algorithm whose average number of steps is bounded between two quadratic functions of the smaller dimension,” Journal of the ACM, vol. 32, no. 4, pp. 871–895, 1985. View at Publisher · View at Google Scholar · View at Scopus
  20. Synopsys 90 nm Library, http://www.synopsys.com/community/universityprogram/pages/library.aspx.
  21. ISPD 2012 cell sizing contest, http://www.ispd.cc/contests/12/ispd2012_contest.html.
  22. X. Yang, B. K. Choi, and M. Sarrafzadeh, “Timing-driven placement using design hierarchy guided constraint generation,” in Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD '02), pp. 177–180, November 2002. View at Publisher · View at Google Scholar · View at Scopus
  23. http://www.ispd.cc/contests/12/ISPD_2012_Contest_Results.pdf.