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VLSI Design
Volume 2013, Article ID 495354, 12 pages
http://dx.doi.org/10.1155/2013/495354
Research Article

Faster and Energy-Efficient Signed Multipliers

VLSI Division, School of Electronics Engineering, VIT University, Vellore 632014, Tamilnadu, India

Received 13 December 2012; Accepted 22 April 2013

Academic Editor: Juan Sanchez-Garcia

Copyright © 2013 B. Ramkumar and Harish M. Kittur. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [2 citations]

The following is the list of published articles that have cited the current article.

  • Supriya Karmakar, John A. Chandy, and Faquir C. Jain, “Unipolar Logic Gates Based on Spatial Wave-Function Switched FETs,” Ieee Transactions On Very Large Scale Integration (Vlsi) Systems, vol. 23, no. 4, pp. 609–618, 2015. View at Publisher · View at Google Scholar
  • Priya Gupta, Anu Gupta, and Abhijit Asati, “Ultra low power MUX based compressors for wallace and dadda multipliers in sub-threshold regime,” American Journal of Engineering and Applied Sciences, vol. 8, no. 4, pp. 702–716, 2015. View at Publisher · View at Google Scholar