A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation

<table>(a) Integrator architecture 1. (b) Integrator architecture 2. (c) Versatile architecture 1. (d) Versatile architecture 2.</table>

VLSI Design

Figure 3: A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation 