Research Article
A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation
Table 2
The profiling of the MPEG-4 SP@L2 decoder.
| | Function |
Intel Pentium 4
Sequence |
ARM Integrator
Sequence |
Integrator (with optimized MC)
Sequence | | Foreman | M-D | Stefan | Foreman | M-D | Stefan | Foreman | M-D | Stefan |
| | MC (%) | 34.4 | 33.5 | 35.9 | 53.3 | 47.5 | 48.7 | 40.4 | 36.8 | 34.1 | | Interpolation (%) | 22.2 | 24.7 | 21.8 | 11.4 | 6.9 | 10.0 | 15.4 | 19.0 | 13.5 | | IDCT (%) | 23.2 | 22.0 | 26.9 | 18.4 | 21.7 | 21.0 | 21.5 | 23.6 | 25.0 | | ED (%) | 9.6 | 11.6 | 9.8 | 6.4 | 13.1 | 8.5 | 6.4 | 7.1 | 7.4 | | Others (%) | 10.6 | 8.2 | 5.6 | 10.4 | 10.9 | 11.8 | 16.4 | 19.6 | 20.1 |
| | Simulation time (fps) | 769.0 | 822.0 | 652.0 | 19.6 | 22.3 | 17.7 | 22.3 | 24.1 | 20.7 |
|
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Pentium platform: CPU 2.8 Ghz, 800 Mhz FSB with Hyper-Threading technology.
Integrator platform: CPU 120 Mhz, 52 Mhz FSB in asynchronous bus mode.
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