Research Article

Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic

Table 1

Comparison of power, delay, and PDP of 8-inverter chain in 10 cycles of charging and discharging.

Power dissipation (μW)
Frequency (MHz)0.01 0.1 1 10 20 33.3 50
CMOS0.09 0.12 0.40 3.32 6.6 10.9 16.4
QSERL0.020.100.663.696.28.9511.7
IQSERL0.010.020.131.924.88.9215.2

Delay (ns)
CMOS55.43.151.371.521.51.481.47
QSERL421052264.49.385.694.103.29
IQSERL1.926.244.532.562.071.81.68

PDP (fJ)
CMOS4.990.380.555.059.916.124.1
QSERL84.252.242.534.635.336.738.5
IQSERL0.020.120.594.929.9416.025.5