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VLSI Design
Volume 2013 (2013), Article ID 785281, 12 pages
Research Article

A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

Department of Information Engineering, Electronics and Telecommunications, Sapienza University of Rome, Via Eudossiana 18, 00184 Rome, Italy

Received 12 September 2012; Revised 2 December 2012; Accepted 5 December 2012

Academic Editor: Meng-Hsueh Chiang

Copyright © 2013 Mauro Olivieri and Antonio Mastrandrea. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [1 citation]

The following is the list of published articles that have cited the current article.

  • Mario R. Casu, and Paolo Mantovani, “A synchronous latency-insensitive RISC for better than worst-case design,” Integration, the VLSI Journal, 2014. View at Publisher ยท View at Google Scholar