VLSI Design

Research Article

LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

Table 4

A comparison of the proposed adaptive decoder using the wordwidth adaptive Method 2 decoder with recently published LDPC decoder implementations.
  Liu and Shi [30] Ueng et al. [31] Mansour and Shanbhag [32] Mohsenin et al. [14] Zhang et al. [15] This work
Technology 90 nm, 8M 90 nm 180 nm 65 nm 65 nm, 7 M 65 nm, 7 M
Implementation P&R P&R Measured P&R Measured P&R
Architecture partial parallel partial parallel partial parallel full parallel partial parallel full parallel
Decoding Alg. SMP Shuffled MPD TDMP Split-Threshold TPMP Adaptive wordwidth1
Code Length 2048 1536–3968 2048 2048 2048 2048
Edges 12288 7680–23808 — 12288 12288 12288
Code Rate 0.84 0.79–0.93 0.5 0.84 0.84 0.84
Bits per message 5 —— 5 4 6
Logic utilization 50% — 50% 95% 80% 96%
Chip area (mm2) 14.5 4.41 14.3 4.55 5.35 5.10
Max. iterations ( ) 16 8, 4 16 11 8 15
Supply voltage (V) — 1.0 1.8 1.3 1.2 0.7 1.3 0.7
Clock speed (MHz) 207 303 125 195 700 100 185 40
Maximum Latency (ns) ——— 56.4 137 960 81 375
Throughput @ (Gbps) 5.3 4.85, 9.7 0.400 36.3 14.92 2.1225.26 5.4
Throughput w/early term. (Gbps) — 4.85, 9.7 6.4 92.8 47.7 6.67 85.7 18.5
Throughput per area (Gbps/mm2) 0.36 11, 22 — 19.1 8.9 1.2 16.8 3.6
Power (mW) — 855 787 1359 2800 144 1172 73
Energy/bit w/early term. (pJ/bit) — 176, 88 — 15 58.7 21.5 13.6 3.9
1This work is also a variant of Split-Threshold method. 2Throughput is computed based on the maximum latency reported. 3Power numbers are for , Method 2.