Journals
Publish with us
Publishing partnerships
About us
Blog
VLSI Design
Table of Contents
Special Issues
VLSI Design
/
2013
/
Article
/
Fig 14
/
Research Article
Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits
Figure 14
Muller C-element: (a) gate level, (b) transistor level.
(a)
(b)