Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits

<table>Comparison of yield analysis results of SB and non-SB for behavioural-level SRAM<svg height="11.125" id="M253" style="vertical-align:-0.1638pt" version="1.1" viewbox="0 0 42.137501 11.125" width="42.137501" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
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</svg> simulations for strongly correlated case, (a) MC and (b) QMC.</table>

VLSI Design

fig23

Figure 23

Figure 23: Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits 