Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits

Table 3

Run times and time savings for MC/QMC simulations of the SRAM32 × 8 array (strongly correlated).

	Transistor model: ngSRAM32 × 8.seed				SBCB model: ngswSRAM32 × 8.seed
	MC		QMC		MC		QMC
	Non-SB	SB	Non-SB	SB	Non-SB	SB	Non-SB	SB
CPU time/s	47263.96	1481.69	39373.99	1183.59	2376.14	63.70	2148.03	69.84
		𝑊 = 13		𝑊 = 0		𝑊 = 6		𝑊 = 0
Time saving	96.87%		96.99%		97.32%		96.75%
Overall time saving = (47263.96−69.84)/47263.96 = 99.85%