Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

Table 1

Comparison of multipliers for delay, power, and area.

Type of multiplier	Delay in ns			Power in mW			Number of LUTs
	32 bit	16 bit	8 bit	32 bit	16 bit	8 bit	32 bit	16 bit	8 bit
Array	76.1	39.9	21	21	11	7	1519	375	91
Booth	86.1	27.99	14.9	25	15	12	1277	317	77
Vedic	70.7	39.02	24.4	28	18	12	2378	565	126