Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

Table 3

Device utilization and timing summary of path solvers.

Path solver name	Device utilization summery		Timing summery			Max. frequency (Hz)
	Logic utilization	Used	Min period in ns	Setup time in ns	Hold time in ns
Critical path solver	Number of slices	5804	9.068 ns	15.72 ns	6.141 ns	110.277
	Number of LUTs	10462
	Number of slice Flipops	3664
Shortest path solver	Number of slices	4147	14.089 ns	10.477 ns	4.114 ns	70.978
	Number of LUTs	7511
	Number of slice Flipops	1496