Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

Table 6

Comparison of area, delay, and power for different models of various digital filters.

Filter block	Adder multipliers Flipflops			DelayMax Freq in MHz			Power in Watts
	Model 1	Model 2	Model 3	Model 1	Model 2	Model 3	Model 1	Model 2	Model 3
FIR-2	5/2/3	5/0/3	5/0/4	51.54	192.14	340.62	0.056	0.063	0.065
FIR-4	10/3/5	11/0/5	11/0/8	59.41	108.41	222.04	0.047	0.057	0.060
FIR-6	7/2/7	17/0/7	17/0/14	62.91	67.64	259.47	0.051	0.062	0.064
FIR-8	15/5/9	22/0/9	22/0/16	54.82	65.92	117.91	0.054	0.058	0.065
FIR-10	18/6/11	25/0/11	25/0/11	48.22	56.37	100.72	0.058	0.061	0.063
FIR-12	20/7/13	29/0/13	29/0/13	46.34	54.86	193.40	0.060	0.063	0.067
IIR-2	9/4/3	11/0/3	11/0/3	55.03	75.53	89.10	0.047	0.050	0.050
IIR-4	16/7/5	20/0/5	19/0/6	22.78	113.88	151.65	0.059	0.062	0.063
IIR-6	24/11/7	35/0/7	35/0/8	38.71	42.54	53.142	0.051	0.059	0.058
IIR-8	30/11/10	33/0/10	33/0/7	29.46	70.14	110.21	0.044	0.064	0.081
IIR-10	37/16/13	54/0/13	54/0/14	36.43	48.85	95.381	0.051	0.067	0.085
IIR-12	42/20/17	63/0/17	63/0/19	39.73	50.74	101.52	0.063	0.071	0.088