TY - JOUR A2 - Fan, Yu-Cheng AU - Panwar, Shikha AU - Piske, Mayuresh AU - Madgula, Aatreya Vivek PY - 2014 DA - 2014/07/15 TI - Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits SP - 380362 VL - 2014 AB - This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption. SN - 1065-514X UR - https://doi.org/10.1155/2014/380362 DO - 10.1155/2014/380362 JF - VLSI Design PB - Hindawi Publishing Corporation KW - ER -