Table of Contents
VLSI Design
Volume 2014, Article ID 380362, 5 pages
Research Article

Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

School of Electronics Engineering (SENSE), VIT University, Vandalur-Kelambakkam Road, Chennai 600127, India

Received 2 May 2014; Accepted 27 June 2014; Published 15 July 2014

Academic Editor: Yu-Cheng Fan

Copyright © 2014 Shikha Panwar et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [2 citations]

The following is the list of published articles that have cited the current article.

  • G. Amuthavalli, R. Gunasundari, G. Amuthavalli, and R. Gunasundari, “Analysis and Design of Subthreshold Leakage Power-Aware Ripple Carry Adder at Circuit-Level using 90nm Technology,” International Conference On Computer, Communication And Convergence (Iccc 2015), vol. 48, pp. 660–665, 2015. View at Publisher · View at Google Scholar
  • Tomar, and Reeya Agrawal, “Analysis of Cache(SRAM) Memory for Core i™ 7 Processor,” 2018 9th International Conference on Computing, Communication and Networking Technologies, ICCCNT 2018, 2018. View at Publisher · View at Google Scholar