Table of Contents Author Guidelines Submit a Manuscript
VLSI Design
Volume 2014, Article ID 406416, 7 pages
http://dx.doi.org/10.1155/2014/406416
Research Article

Optimization of Fractional-N-PLL Frequency Synthesizer for Power Effective Design

1Department of Electronic Engineering, University College of Engineering and Technology, The Islamia University of Bahawalpur, Bahawalpur 63100, Pakistan
2Scholar Teacher Research Alliance for Problem Solving (STRAPS), Bahawalpur 63100, Pakistan
3Department of Computer System Engineering, University College of Engineering and Technology, The Islamia University of Bahawalpur, Bahawalpur 63100, Pakistan

Received 10 May 2014; Accepted 7 June 2014; Published 23 July 2014

Academic Editor: Yu-Cheng Fan

Copyright © 2014 Sahar Arshad et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. R. Jacob Baker, CMOS Circuit Design, Layout and Simulation, IEEE Press, John Wiley & Sons, 3rd edition, 2010.
  2. A. Anil and R. K. Sharma, “A high efficiency charge pump for low voltage devices,” International Journal of VLSI Design & Communication Systems, vol. 3, no. 3, 2012. View at Google Scholar
  3. U. L. Rohde, Digital PLL Frequency Synthesis, Prentice-Hall, Englewood Cliffs, NJ, USA, 1983.
  4. B. K. Mishra, S. Save, and S. Patil, “Design and analysis of second and third order PLL at 450 MHz,” International Journal of VLSI Design & Communication Systems, vol. 2, no. 1, 2011. View at Google Scholar
  5. N. Weste and D. Harris, CMOS VLSI Design—A Circuits and Systems Perspective, Pearson Education, 3rd edition, 2005.
  6. U. A. Belorkar and S. A. Ladhake, “Design of low power phase lock loop using 45 nm VLSI technology,” International Journal of VLSI Design & Communication Systems, vol. 1, no. 2, 2010. View at Google Scholar
  7. T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewski, “Delta-Sigma modulation in fractional-n frequency synthesis,” IEEE Journal of Solid-State Circuits, vol. 28, no. 5, pp. 553–559, 1993. View at Publisher · View at Google Scholar · View at Scopus
  8. M. H. Perrott, “Fractional-N Frequency Synthesizer Design Using The PLL Design Assistant and CppSim Programs,” July 2008.
  9. S. Franssila, Introduction to Microfabrication, John Wiley & Sons, 2004.
  10. K. Woo, Y. Liu, E. Nam, and D. Ham, “Fast-lock hybrid PLL combining fractional-N and integer-N modes of differing bandwidths,” IEEE Journal of Solid-State Circuits, vol. 43, no. 2, pp. 379–389, 2008. View at Publisher · View at Google Scholar · View at Scopus
  11. N. Fatahi and H. Nabovati, “Design of low noise fractional-N frequency synthesizer using sigma-delta modulation technique,” in Proceedings of the 27th International Conference on Microelectronics (MIEL '10), pp. 369–372, IEEE, May 2010. View at Publisher · View at Google Scholar · View at Scopus
  12. S. Borkar, “Obeying Moore's law beyond 0.18 micron,” in Proceedings of the 13th Annual IEEE International ASIC/SOC Conference, pp. 26–31, September 2000. View at Scopus
  13. R. K. Krishnamurthy, A. Alvandpour, V. De, and S. Borkar, “High-performance and low-power challenges for sub-70 nm microprocessor circuits,” in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 125–128, May 2002. View at Scopus