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VLSI Design
Volume 2014, Article ID 451310, 9 pages
http://dx.doi.org/10.1155/2014/451310
Research Article

Improved Quantization Error Compensation Method for Fixed-Width Booth Multipliers

School of Electronics and Information Engineering, Xi’an Jiaotong University, Xi’an 710049, China

Received 13 September 2013; Accepted 22 December 2013; Published 6 February 2014

Academic Editor: M. Renovell

Copyright © 2014 Xiaolong Ma et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. J. M. Jou, S. R. Kuang, and R. D. Chen, “Design of low-error fixed-width multipliers for DSP applications,” IEEE Transactions on Circuits and Systems II, vol. 46, no. 6, pp. 836–842, 1999. View at Publisher · View at Google Scholar · View at Scopus
  2. S.-J. Jou and H.-H. Wang, “Fixed-width multiplier for DSP application,” in Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors (ICCD ’00), pp. 318–322, Austin, Texas, USA, September 2000. View at Scopus
  3. Y.-H. Chen, T.-Y. Chang, and R.-Y. Jou, “A statistical error-compensated Booth multipliers and its DCT applications,” in Proceedings of the IEEE Region 10 Conference (TENCON '10), pp. 1146–1149, Fukuoka, Japan, November 2010. View at Publisher · View at Google Scholar · View at Scopus
  4. M. J. Schulte and E. E. Swartzlander, “Truncated multiplication with correction constant,” in Proceedings of the IEEE Workshop on VLSI Signal Processing VI, pp. 388–396, Veldhoven, The Netherlands, October 1993.
  5. E. J. King and E. E. Swartzlander, “Data-dependent truncated scheme for parallel multiplication,” in Proceedings of the 31st Asilo-mar Conference on Signals, Systems & Computers, pp. 1178–1182, Pacific Grove, Calif, USA, November 1997.
  6. J. E. Stine and O. M. Duverne, “Variations on truncated multiplication,” in Proceedings of the Euromicro Symposium on Digital System Design, pp. 112–119, Belek-Antalya, Turkey, September 2003.
  7. L.-D. Van and C.-C. Yang, “Generalized low-error area-efficient fixed-width multipliers,” IEEE Transactions on Circuits and Systems I, vol. 52, no. 8, pp. 1608–1619, 2005. View at Publisher · View at Google Scholar · View at Scopus
  8. N. Petra, D. De Caro, V. Garofalo, E. Napoli, and A. G. M. Strollo, “Truncated binary multipliers with variable correction and minimum mean square error,” IEEE Transactions on Circuits and Systems I, vol. 57, no. 6, pp. 1312–1325, 2010. View at Publisher · View at Google Scholar · View at Scopus
  9. M.-A. Song, L.-D. Van, and S.-Y. Kuo, “Adaptive low-error fixed-width Booth multipliers,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. 90, no. 6, pp. 1180–1187, 2007. View at Publisher · View at Google Scholar · View at Scopus
  10. K.-J. Cho, K.-C. Lee, J.-G. Chung, and K. K. Parhi, “Design of low-error fixed-width modified booth multiplier,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 5, pp. 522–531, 2004. View at Publisher · View at Google Scholar · View at Scopus
  11. J.-P. Wang, S.-R. Kuang, and S.-C. Liang, “High-accuracy fixed-width modified booth multipliers for lossy applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 1, pp. 52–60, 2011. View at Publisher · View at Google Scholar · View at Scopus
  12. Y.-H. Chen and T.-Y. Chang, “A high-accuracy adaptive conditional-probability estimator for fixed-width Booth multipliers,” IEEE Transactions on Circuits and Systems, vol. 59, no. 3, pp. 594–603, 2012. View at Publisher · View at Google Scholar · View at Scopus
  13. Y.-H. Chen, C.-Y. Li, and T.-Y. Chang, “Area-effective and power-efficient fixed-width booth multipliers using generalized probabilistic estimation bias,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 1, no. 3, pp. 277–288, 2011. View at Publisher · View at Google Scholar · View at Scopus
  14. O. L. MacSorley, “High-speed arithmetic in binary computers,” Proceedings of IRE, vol. 49, no. 1, pp. 67–91, 1961. View at Google Scholar
  15. G. W. Bewick, Fast Multiplication: Algorithms and Implementation, Stanford University, Palo Alto, Calif, USA, 1994.
  16. R. Tandra and A. Sahai, “SNR walls for signal detection,” IEEE Journal on Selected Topics in Signal Processing, vol. 2, no. 1, pp. 4–17, 2008. View at Publisher · View at Google Scholar · View at Scopus