Design of Smart Power-Saving Architecture for Network on Chip

<table><svg height="8.80632pt" id="M32" version="1.1" viewbox="0 -8.80632 10.3644 8.80632" width="10.3644pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.0135,0,0,-0.0135,0,0)"><path d="M748 650H522L515 622L546 617C580 611 587 604 565 575C518 513 469 451 419 393C376 474 349 534 330 580C318 609 325 612 361 618L383 622L392 650H151L144 622C214 616 224 612 257 543L360 327C270 218 187 124 159 95C106 40 92 34 26 28L17 0H252L259 28L236 31C189 37 188 47 209 78C249 136 308 210 377 294L478 79C494 44 487 37 449 32L418 28L409 0H673L680 28C596 34 591 39 554 116L436 361C526 469 574 521 604 553C659 612 669 614 739 622L748 650Z" id="g113-89"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="765" vert-adv-y="765"></glyph.data></g></svg>-<svg height="8.80632pt" id="M33" version="1.1" viewbox="0 -8.80632 8.83342 8.80632" width="8.83342pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.0135,0,0,-0.0135,0,0)"><path d="M640 650H413L406 622L438 617C475 611 483 605 463 571C422 503 346 400 296 333C264 403 215 529 199 575C189 604 191 614 228 618L262 622L271 650H30L23 622C90 615 97 609 119 553L212 321C222 295 223 285 218 259L193 127C176 39 167 33 82 28L76 0H350L356 28C266 36 257 40 275 127L303 266C308 290 314 302 328 322C396 418 454 493 498 546C551 610 565 616 631 622L640 650Z" id="g113-90"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="652" vert-adv-y="652"></glyph.data></g></svg> routing flow chart.</table>

VLSI Design

Design of Smart Power-Saving Architecture for Network on Chip

Figure 5