High-Efficient Circuits for Ternary Addition

Table 10

Simulation results of the new THA with MOSFET and CNTFET technologies.

Design	Delay; (psec)	Power; (μW)	PDP; (fJ)	#Transistors	Total width; (nm)
The proposed THA with MOSFET technology	1248	8.257	10.30	76	12762
The proposed THA with CNTFET technology	28.42	0.880	0.025	64	3840