Figure 2: Embedded system that allows for DPR and dynamic frequency control. (a) Block diagram. The uBlaze and peripherals run at 100 MHz. (b) Frequency and PR control. The Dynamic Reconfiguration Port (DRP) is shown in blue. The external system clock is the reference clock. (c) Real/complex FIR filter processor as a PLB peripheral. Four modes supported: (i) real input, real coefficients, (ii) real input, complex coefficients, (iii) complex input, real coefficients, and (iv) complex input, complex coefficients. Three I/O cases supported: , , and , . The PRR includes the filter IP and the I/O interface to the FIFOs. Two extra parameters can be controlled at run-time: input stream length ( ) and style (basic, centered, full, and streaming).