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VLSI Design
Volume 2014, Article ID 652187, 11 pages
http://dx.doi.org/10.1155/2014/652187
Research Article

Efficient Hardware Trojan Detection with Differential Cascade Voltage Switch Logic

Department of Electrical and Computer Engineering, University of New Hampshire, Durham, NH 03824, USA

Received 26 February 2014; Accepted 7 April 2014; Published 11 May 2014

Academic Editor: Chih-Cheng Lu

Copyright © 2014 Wafi Danesh et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [5 citations]

The following is the list of published articles that have cited the current article.

  • Samer Moein, Salman Khan, T. Aaron Gulliver, Fayez Gebali, and M. Watheq El-Kharashi, “An attribute based classification of hardware trojans,” 2015 Tenth International Conference on Computer Engineering & Systems (ICCES), pp. 351–356, . View at Publisher · View at Google Scholar
  • Papa-Sidy Ba, Sophie Dupuis, Manikandan Palanichamy, Marie-Lise-Flottes, Giorgio Di Natale, and Bruno Rouzeyre, “Hardware Trust through Layout Filling: A Hardware Trojan Prevention Technique,” 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 254–259, . View at Publisher · View at Google Scholar
  • Hao Chen, Tao Wang, Fan Zhang, Xinjie Zhao, Wei He, Lumin Xu, and Yunfei Ma, “Stealthy Hardware Trojan Based Algebraic Fault Analysis of HIGHT Block Cipher,” Security and Communication Networks, vol. 2017, pp. 1–15, 2017. View at Publisher · View at Google Scholar
  • Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, and Bruno Rouzeyre, “Protection Against Hardware Trojans With Logic Testing: Proposed Solutions and Challenges Ahead,” IEEE Design & Test, vol. 35, no. 2, pp. 73–90, 2018. View at Publisher · View at Google Scholar
  • Imran Hafeez Abbassi, Faiq Khalid, Osman Hasan, Awais Mehmood Kamboh, and Muhammad Shafique, “McSeVIC: A Model Checking Based Framework for Security Vulnerability Analysis of Integrated Circuits,” IEEE Access, vol. 6, pp. 32240–32257, 2018. View at Publisher · View at Google Scholar