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VLSI Design
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2014
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Article
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Fig 11
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Research Article
On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding
Figure 11
Comparison of % of power savings between different serialization factors with different cache bus width.
(a)
8-core set 1
(b)
4-core set 1
(c)
2-core set 1