Research Article

On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding

Figure 19

(a) % of performance degradation in term of instruction per cycle (IPC) for using 64-bit serialized bus with encoding for 2/1 cycle performance penalty instead of using conventional bus and (b) % of power savings.
801241.fig.0019a
(a)
801241.fig.0019b
(b)