Table of Contents
VLSI Design
Volume 2015, Article ID 264071, 13 pages
Research Article

A Novel Scan Architecture for Low Power Scan-Based Testing

Department of Electronic Systems Engineering, Malaysia-Japan International Institute of Technology, Universiti Teknologi Malaysia, Jalan Sultan Yahya Petra, 54100 Kuala Lumpur, Malaysia

Received 27 November 2014; Revised 12 March 2015; Accepted 26 March 2015

Academic Editor: Jose Carlos Monteiro

Copyright © 2015 Mahshid Mojtabavi Naeini and Chia Yee Ooi. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [6 citations]

The following is the list of published articles that have cited the current article.

  • Sinduja, Siddharth Raghav, and Anita, “Efficient don't-care filling method to achieve reduction in test power,” 2015 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2015, pp. 478–482, 2015. View at Publisher · View at Google Scholar
  • Chia Yee Ooi, Tomokazu Yoneda, Mahshid Mojtabavi Naeini, Sreedharan Baskara Dass, and Michiko Inoue, “An integrated DFT solution for power reduction in scan test applications by low power gating scan cell,” Integration, the VLSI Journal, vol. 57, pp. 108–124, 2017. View at Publisher · View at Google Scholar
  • Sanjoy Mitra, and Debaprasad Das, “An Inter-Test Cube Bit Stream Connectivity-Optimized X-Filling Approach Aiming Shift Power Reduction,” International Conference on Intelligent Computing and Applications, vol. 632, pp. 477–487, 2017. View at Publisher · View at Google Scholar
  • Taehee Lee, and Joon-Sung Yang, “Physical-aware gating element insertion for thermal-safe scan shift operation,” IEICE Electronics Express, 2017. View at Publisher · View at Google Scholar
  • Heetae Kim, Hyunggoy Oh, Jaeil Lim, and Sungho Kang, “A novel X-filling method for capture power reduction,” IEICE Electronics Express, vol. 14, no. 23, pp. 20171093–20171093, 2017. View at Publisher · View at Google Scholar
  • Kyongjun Noh, Taehee Lee, and Jun Dong Cho, “Functional-power-aware partial gating method for low power scan-shift,” Journal of Semiconductor Technology and Science, vol. 18, no. 1, pp. 125–129, 2018. View at Publisher · View at Google Scholar