VLSI Design

VLSI Design / 2015 / Article / Tab 1

Research Article

A Novel Scan Architecture for Low Power Scan-Based Testing

Table 1

Comparison of total power consumption during shift and normal/capture mode.

Prop. scan cellFLS scan cell Partial MUX gating scan cellNOR gating scan cellModified scan cell Conventional scan cell
Power con. (W)Power con. (W)% imp. overPower con. (W)% imp. overPower con. (W)% imp. overPower con. (W)% imp. overPower con. (W)% imp. over

Ave. total power

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