VLSI Design

VLSI Design / 2015 / Article / Tab 2

Research Article

A Novel Scan Architecture for Low Power Scan-Based Testing

Table 2

Comparison of average power consumption during shift mode.

Prop. scan cell% imp.FLS scan cell% imp.Partial MUX gating scan cell% imp.NOR gating scan cell% imp.Modified scan cell% imp.

Avg. power (W)Shift cycle #1
Shift cycle #2
Shift cycle #3
Shift cycle #4

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